A liquid crystal display typically comprises an active plate and a passive plate between which liquid crystal material is sandwiched. The active plate comprises an array of transistor switching devices, typically with one transistor associated with each pixel of the display. Each pixel is also associated with a pixel electrode on the active plate to which a signal is applied for controlling the brightness of the individual pixel.
A large area of the active plate is at least partially transparent, and this is required because the display is typically illuminated by a back light. Mainly, the areas covered by the opaque row and column conductors are the only opaque parts of the plate. If the pixel electrode does not cover the transparent area, then there will be an area of liquid crystal material not modulated by the pixel electrode but which does receive light from the back light. This reduces the contrast of the display. A black mask layer is typically provided for shielding these areas of the active plate, and additionally to shield the transistors as their operating characteristics are light-dependent. Conventionally, the black mask layer is located on the passive plate of the active matrix cell. However, the overlap between the black mask layer and the pixel electrodes needs to be large in this case as a result of poor cell coupling accuracy. This overlap reduces the aperture of the display pixels, which reduces the power efficiency of the display. This is particularly undesirable for battery operated devices, such as portable products.
It has been proposed to use layers of the active plate to provide the required masking function. For example, one proposal is to define the pixel electrodes to overlap the row and column conductors, so that there is no gap between the row and column conductors and the pixel electrodes, which would otherwise need to be shielded. FIG. 1 illustrates the essential process steps for manufacturing an active plate in this way.
FIG. 1A shows a patterned gate conductor layer 10, which defines a transistor gate 12 which is connected to an associated row conductor 14. A gate insulator layer overlies the patterned gate conductor layer and a semiconductor layer is deposited over the insulated gate structure. The semiconductor layer is patterned to define the semiconductor body 16 of the transistor, as well as an insulator layer 18 to reduce capacitive coupling at the cross-over between row and column conductors. The patterned semiconductor layer 16,18 is shown in FIG. 1B.
A source and drain conductor layer is deposited and patterned over the silicon layer which defines a transistor source 20 connected to a column conductor 22, and a drain region 24. As shown in FIG. 1C, the region 18 provides insulation at the cross-over of the row 14 and column 22 conductors. The source and drain conductor layer also defines a capacitor top contact 26. This is a pixel charge storage capacitor defined by the row conductor 14, the gate insulator layer and the top contact 26.
As shown in FIG. 1D a passivation layer is deposited over the entire structure and through-holes 28, 30 are provided to enable connection through the passivation layer to the drain 24 and to the capacitor top contact 26. Finally, the pixel electrodes 32, 34 are deposited over the passivation layer with each pixel electrode making contact through the through-holes 28, 30 to a drain 24 of the associated switching transistor and to the top contact 26 of the pixel charged storage capacitor.
FIG. 2 shows the electrical components which make up the pixels shown in FIG. 1. The row conductor 14 is connected to the gate of the TFT 40, and the column electrode 22 is coupled to the source, as explained with reference to FIG. 1. The liquid crystal material provided over the pixel effectively defines a liquid crystal cell 42 which extends between the drain of the transistor 40 and a common ground plane 44. The pixel storage capacitor 46 is connected between the drain of the transistor 40 and the row conductor 14a associated with an adjacent row of pixels.
In the process described with reference to FIG. 1, the row and column electrodes are used to provide masking of the pixel. In particular, the overlap of the pixel electrodes 32 and 34 over the row and column conductors eliminates any gap which requires shielding. This means that there is no need to provide a black mask layer on the passive plate to define each pixel. Since a black mask layer on the passive plate cannot be aligned exactly with the pixels on the active plate a black mask layer on the passive plate would need to have a significant overlap with the row and column conductors. Therefore, the omission of the mask layer on the passive plate delivers a liquid crystal display in which each pixel has a large aperture.
Another way of providing a masking function on the active plate is described in U.S. Pat. No. 5,781,254 to Kim et al. Referring to FIG. 3, a transistor has a gate 12 is provided under a channel 16 connected between source 20 and drain 24. The drain is connected to a transparent pixel electrode 32. Row 14 and column 22 electrodes connect a plurality of transistors and pixel electrodes in an array. In this arrangement, an organic masking layer 48 is provided over the row and column electrodes, and the transistor region, as shown in FIG. 4.
U.S. Pat. No. 5,121,237 to Ikeda et al describes a liquid crystal display in which an organic mask layer is provided over a channel region of an active substrate to protect the channel region from light. The masking around the individual pixels is provided on the passive substrate. A further document disclosing the use of an organic mask layer to protect a thin film transistor structure is U.S. Pat. No. 5,703,668 to Shin et al. The mask layer is deposited above an oxide or nitride layer that covers the channel.
The structures described above are all “bottom gate” structures in which the gate 12 lies under the channel 16. An alternative form of structure is a top-gate structure in which the gate lies above the channel. One advantage of such a structure is that since the gate electrode lies on top of the transistor the material and thickness of the gate electrode may be selected with more freedom.
FIG. 5 illustrates a known top-gate structure in cross section. A metal light shield layer 53 is deposited on a transparent substrate 51 as will be explained below. A silicon dioxide layer is deposited to separate the rest of the structure from the metal layer 53. Then, a thin-film transistor (TFT) structure is deposited. Firstly, a transparent electrode layer 57 is provided to act as pixel electrodes 59. A column conductor 61 is deposited on this layer. An amorphous silicon (a-Si:H) layer 63 acting as source, drain and channel of the TFT is deposited, followed by first 65 and second 67 silicon nitride layers. A gate electrode 69 is deposited on top of the structure, and connected to row conductors (not shown).
The channel of the TFT may be photosensitive and so it is desirable to prevent light reaching it. The top gate may provide the necessary shielding from above. However, many liquid crystal displays are back-lit, i.e. lit from below, and so the metal layer 53 is patterned to be present under the TFT to shield the TFT from light from below.
Unfortunately, it is not possible to use the metal layer 53 that shields the TFT as a mask layer to prevent light passing through the liquid crystal display between pixels. This is because the mask layer would have to surround each pixel which would result in a continuous mesh covering the whole of the display. Such an electrically continuous mesh would lead to undesirable capacitative couplings with and between other conductors on the active substrate, leading to degradation of performance. Therefore in conventional LCD top-gate TFT devices a mask layer is provided on the passive plate to separate each pixel, as in conventional bottom-gate structures.
It would be beneficial if the mask layer could be eliminated. The structures discussed above, which are designed to eliminate the mask layers from bottom gate TFTs, provide mask layers over the bottom gate TFTs that both shield the channels of the TFTs and also act as mask layers. These structures are not suitable for top-gate TFTs, in which the top gate itself provides some shielding from light from above and it is instead light from below that needs to be prevented.
A further disadvantage of conventional top-gate TFT structures is that the metallic light shield layer is effectively a floating gate that can store charge and slowly leak it. The stored charge can affect the channel region of the TFT by variable amounts which can significantly affect the turn-on and turn-off voltages of the TFT. Since consistency of turn-on and turn-off voltages is important to the performance of the device, the floating gate effect of the light shield layer is highly detrimental. Accordingly, it would be of benefit if this effect could be minimized.